1. Field of the Invention
The present invention generally relates to phase lock loop circuits. More particularly, the present invention relates to the field of lock detector circuits, without having an external capacitor to specify a desired phase error, for determining phase lock condition in a phase lock loop circuit.
2. Related Art
Phase lock loop (PLL) circuits have been one of the basic building blocks in modern electronic systems. They have been widely used in communications, multimedia, and other applications. Frequency synthesizers, FM demodulators, clock recovery circuits, data synchronizers, modems, and tone decoders are some applications for PLLs.
PLLs are negative feedback control systems. A PLL generally comprises a phase-frequency detector, a charge pump, a low pass filter, a voltage-controlled oscillator (VCO), and a frequency divider. The phase-frequency detector generates an up signal and/or a down signal based on the difference in phase (and frequency) between a reference signal and a feedback signal. The phase-frequency detector is followed by the charge pump and the low pass filter. Continuing, these components provide a DC signal based on the up signal and/or the down signal from the phase-frequency detector. The voltage-controlled oscillator (VCO) follows the low pass filter. In particular, the VCO generates a high frequency VCO output signal controlled by the DC signal. Then, the frequency divider generates the low frequency feedback signal based on the high frequency VCO output signal. The feedback signal is fed to an input of the phase-frequency detector. In an in-lock mode of the PLL, the reference signal and the feedback signal are locked in phase (and frequency). In an out-of-lock mode of the PLL, the reference signal and the feedback signal are not locked in phase (and frequency).
An important aspect of PLL design is the lock detector circuit. The lock detector circuit generates a lock signal to indicate whether the PLL is operating in a in-lock mode or in a out-of-lock mode. FIG. 1 illustrates a conventional lock detector circuit 50 according to the prior art. As depicted in FIG. 1, the conventional lock detector circuit 50 receives the up signal 10 and the down signal 20 from the phase-frequency detector and generates the lock signal 30. Typically, a HIGH level lock signal 30 indicates an in-lock mode while a LOW level lock signal 30 indicates an out-of-lock mode. Typically, the PLL can make the phase difference between the reference signal and the feedback signal very small or can align these phases. However, parasitic losses, noisy systems, jitter, and other sources increase the phase difference between the reference signal and the feedback signal and prevent these signals from becoming synchronized. Depending on the application, a phase error is usually defined because perfect synchronization between the phases of the reference signal and the feedback signal is not always necessary. Generally, a phase difference of greater magnitude than the phase error corresponds to a PLL in an out-of-lock mode. Similarly, a phase difference of lesser magnitude than the phase error corresponds to a PLL in an in-lock mode.
As shown in FIG. 1, an external capacitor CLD is coupled to the conventional lock detector circuit 50. The external capacitor CLD is utilized to specify the phase error. In particular, the value of the external capacitor CLD is selected to correspond with the desired phase error (i.e., an acceptable pulse width in the up signal 10 and/or down signal 20 that does not cause the conventional lock detector circuit 50 to indicate the PLL is in an out-of-lock mode). Thus, if the phase difference (as indicated by the up signal 10 and/or down signal 20) between the reference signal and the feedback signal is no greater than the desired phase error, the lock signal 30 will have a HIGH level to indicate the PLL is in an in-lock mode. In contrast, if the phase difference (as indicated by the up signal 10 and/or down signal 20) between the reference signal and the feedback signal is greater than the desired phase error, the lock signal 30 will have a LOW level to indicate the PLL is in an out-of-lock mode. Generally, when the phase difference between the reference signal and the feedback signal has a small magnitude, the phase-frequency detector generates the up signal 10 and/or down signal 20 having a short pulse width. The external capacitor CLD is used to form a filter to remove short pulses (or ripples) from the up signal 10 and/or down signal 20, whereas these short pulses are removed because they are within the tolerance level specified by the desired phase error.
A lock detector circuit for a phase lock loop (PLL) circuit is described. The lock detector circuit determines and indicates whether the PLL is in an in-lock mode or in an out-of-lock mode without having an external capacitor for controlling phase error. Moreover, the lock detector circuit indicates the operating mode of the PLL on a period-by-period basis relative to the period of the reference and feedback signals. Thus, the lock detector circuit provides real-time indication of the operating mode of the PLL.
In an embodiment, the lock detector circuit is coupled to an up signal and a down signal from the PLL, whereas the up and down signals indicate the phase difference between the reference signal and the feedback signal. The lock detector circuit generates a first signal representing a non-overlapping portion of the up and down signals. Moreover, the lock detector circuit adds time delay to the first signal to form a second signal, whereas the time delay is dependent on a desired phase error between the reference and feedback signals. In an embodiment, one or more D-type flip-flops arranged in series provide the time delay, whereas the D-type flip-flops are clocked by the VCO output signal generated by the voltage-controlled oscillator (VCO) of the PLL. Next, a third signal is generated, whereas the third signal indicates whether the first and second signals overlap. Continuing, the lock detector circuit detects the period of the reference and feedback signals and generates an output signal using the third signal to indicate on a period-by-period basis the operating mode of the PLL, whereas the output signal indicates the operating mode within a tolerance level specified by the desired phase error.
These and other advantages of the present invention will no doubt become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.